8T49N285_16 Datasheet, PDF (19/67 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N285 Datasheet
Table 6F. Digital PLL Feedback Control Register Bit Field Locations and Descriptions
Digital PLL Feedback Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
0017
M1_0[23:16]
0018
M1_0[15:8]
0019
M1_0[7:0]
001A
M1_1[23:16]
001B
M1_1[15:8]
001C
M1_1[7:0]
001D
Rsvd
001E
Rsvd
001F
Rsvd
0020
Rsvd
0021
Rsvd
0022
Rsvd
0023
LCKBW[3:0]
ACQBW[3:0]
0024
LCKDAMP[2:0]
ACQDAMP[2:0]
PLLGAIN[1:0]
0025
Rsvd
Rsvd
Rsvd
Rsvd
0026
Rsvd
0027
Rsvd
0028
Rsvd
Rsvd
0029
Rsvd
002A
Rsvd
002B
FFh
002C
FFh
002D
FFh
002E
FFh
002F
SLEW[1:0]
Rsvd
HOLD[1:0]
Rsvd
HOLDAVG FASTLCK
0030
LOCK[7:0]
0031
Rsvd
DSM_INT[8]
0032
DSM_INT[7:0]
0033
Rsvd
DSMFRAC[20:16]
0034
DSMFRAC[15:8]
0035
DSMFRAC[7:0]
0036
Rsvd
0037
01h
0038
Rsvd
0039
Rsvd
003A
DSM_ORD[1:0]
DCXOGAIN[1:0]
Rsvd
DITHGAIN[2:0]
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Revision 5, October 26, 2016