8T49N285_16 Datasheet, PDF (21/67 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N285 Datasheet
Digital PLL Feedback Configuration Register Block Field Descriptions
Bit Field Name Field Type Default Value Description
SLEW[1:0]
R/W
Phase-slope control for Digital PLL:
00 = no limit - controlled by loop bandwidth of Digital PLL¹
00b
01 = 83 µsec / sec
10 = 13 µsec / sec
11 = Reserved
HOLD[1:0]
R/W
HOLDAVG
R/W
Holdover Averaging mode selection for Digital PLL:
00 = Instantaneous mode - uses historical value 100ms prior to entering holdover
00b
01 = Fast Average Mode
10 = Reserved
11 = Set VCO control voltage to V_CC/2
Holdover Averaging Enable for Digital PLL:
0b
0 = Holdover averaging disabled
1 = Holdover averaging enabled as defined in HOLD[1:0]
FASTLCK
R/W
Enables Fast Lock operation for Digital PLL:
0b
0 = Normal locking using LCKBW & LCKDAMP fields in all cases
1 = Fast Lock mode using ACQBW & ACQDAMP when not phase locked and LCKBW
& LCKDAMP once phase locked
LOCK[7:0]
R/W
3Fh
Lock window size for Digital PLL. Unsigned 2’s complement binary number in steps of
2.5ns, giving a total range of 640ns. Do not program to 0.
DSM_INT[8:0]
R/W
DSMFRAC[20:0]
R/W
02Dh
000000h
Integer portion of the Delta-Sigma Modulator value. Do not set higher than FFh. This
implies that for crystal frequencies lower than 16MHz, the doubler circuit must be
enabled.
Fractional portion of Delta-Sigma Modulator value. Divide this number by 2²¹ to
determine the actual fraction.
DSM_ORD[1:0]
R/W
Delta-Sigma Modulator Order for Digital PLL:
00 = Delta-Sigma Modulator disabled
11b
01 = 1st order modulation
10 = 2nd order modulation
11 = 3rd order modulation
DCXOGAIN[1:0]
R/W
Multiplier applied to instantaneous frequency error before it is applied to the Digitally
Controlled Oscillator in Digital PLL:
01b
00 = 0.5
01 = 1
10 = 2
11 = 4
DITHGAIN[2:0]
R/W
000b
Dither Gain setting for Digital PLL:
000 = no dither
001 = Least Significant Bit (LSB) only
010 = 2 LSBs
011 = 4 LSBs
100 = 8 LSBs
101 = 16 LSBs
110 = 32 LSBs
111 = 64 LSBs
Rsvd
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
NOTE 1: Settings other than “00” may result in a significant increase in initial lock time.
©2016 Integrated Device Technology, Inc.
21
Revision 5, October 26, 2016