ICS8S89833I Datasheet, PDF (2/16 Pages) Integrated Device Technology – Four differential LVDS outputs

ICS8S89833I Data Sheet
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/INTERNAL TERMINATION
Table 1. Pin Descriptions
Number
1, 2
Name
Q0, nQ0
Type
Output
3, 4
Q1, nQ1 Output
5, 6
Q2, nQ2 Output
Description
Differential output pair. Normally terminated with 100Ω across the pair. LVDS interface
levels.
Differential output pair. Normally terminated with 100Ω across the pair. LVDS interface
levels.
Differential output pair. Normally terminated with 100Ω across the pair. LVDS interface
levels.
7, 14
8
9
10
11
12
13
15, 16
V_DD
EN
nIN
V_{REF_AC}
V_T
IN
GND
Q3, nQ3
Power
Input
Input
Output
Input
Input
Power
Output
Pullup
Power supply pins.
Synchronizing output enable pin. When LOW, disables outputs. When HIGH, enables
outputs. Internally connected to a 37kΩ pullup resistor. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50Ω termination to V_T.
Reference voltage for AC-coupled applications. Equal to V_DD - 1.4V (approx.). Maximum
sink/source current is ±2mA.
Input termination center-tap. Each side of the differential input pair terminates to a V_T pin.
The V_T pins provide a center-tap to a termination network for maximum interface flexibility.
Non-inverting differential clock input. RT = 50Ω termination to V_T.
Power supply ground.
Differential output pair. Normally terminated with 100Ω across the pair. LVDS interface
levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
R_PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
kΩ
ICS8S89833AKI REVISION A JULY 13, 2010
2
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