ICS8S89833I Datasheet, PDF (1/16 Pages) Integrated Device Technology – Four differential LVDS outputs

Low Skew, 1-To-4 Differential-To-LVDS
Fanout Buffer w/Internal Termination
ICS8S89833I
DATA SHEET
General Description
The ICS8S89833I is a high speed 1-to-4 Differential-to-LVDS Fanout
Buffer with Internal Termination. The ICS8S89833I is optimized for
high speed and very low output skew, making it suitable for use in
demanding applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The internally terminated differential
input and VREF_AC pin allow other differential signal families such as
LVPECL, LVDS, and CML to be easily interfaced to the input with
minimal use of external components. The device also has an output
enable pin which may be useful for system test and debug purposes.
The ICS8S89833I is packaged in a small 3mm x 3mm 16-pin
VFQFN package which makes it ideal for use in space-constrained
applications.
Features
• Four differential LVDS outputs
• IN, nIN input pair can accept the following differential input levels:
LVPECL, LVDS, CML
• Output frequency: 2GHz
• Cycle-to-cycle jitter, RMS: 3.5ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• Output skew: 30ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Propagation Delay: 600ps (maximum)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
IN
50Ω
V_T
50Ω
nIN
V_{REF_AC}
EN ^Pullup
DQ
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q0 1
12 IN
nQ0 2
11 VT
Q1 3
10 VREF_AC
nQ1 4
9 nIN
5 6 78
ICS8S89833I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89833AKI REVISION A JULY 13, 2010
1
©2010 Integrated Device Technology, Inc.