ICS8S89831I Datasheet, PDF (2/21 Pages) Integrated Device Technology – Output frequency

ICS8S89831I Data Sheet
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
Type
Output
Output
Output
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
7, 14
8
9
10
11
12
13
15, 16
V_cc
EN
nIN
V_{REF_AC}
V_T
IN
V_EE
Q0, nQ0
Power
Input
Input
Output
Input
Input
Power
Output
Pullup
Power supply pins.
Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will
go HIGH on the next LOW transition at IN input. Input threshold is V_CC/2. Includes a
37kΩ pull-up resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50Ω termination to V_T.
Reference voltage for AC-coupled applications.
Termination input. I_{REF_AC} (max.) < ±2mA.
Non-inverting LVPECL differential clock input.
RT = 50Ω termination to V_T.
Negative supply pin.
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
R_PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
kΩ
ICS8S89831AKI REVISION A APRIL 26, 2010
2
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