ICS8S89831I Datasheet, PDF (15/21 Pages) Integrated Device Technology – Output frequency

ICS8S89831I Data Sheet
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8S89831I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8S89831I is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for V_CC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.465V * 45mA = 155.925mW
• Power (outputs)_MAX = 32.94mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32.94mW = 131.76mW
• Power Dissipation for internal termination R_T
Power (R_T)_MAX = (V_{IN_MAX})² / R_{T_MIN} = (1.2V)² / 80Ω = 18mW
Total Power__MAX (3.3V, with all outputs switching) = 155.925mW + 131.76mW + 18mW = 305.685mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.306W * 74.7°C/W = 107.9°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θ_JA for 16 Lead VFQFN, Forced Convection
θ_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
1
65.3°C/W
2.5
58.5°C/W
ICS8S89831AKI REVISION A APRIL 26, 2010
15
©2010 Integrated Device Technology, Inc.