ICS859S0412I Datasheet, PDF (2/23 Pages) Integrated Device Technology – Maximum output frequency

ICS859S0412I Data Sheet
4:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
Name
Type
Description
1,
20
CLK_SEL1,
CLK_SEL0
Input
Pulldown Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
2
PCLK0
Input
Pulldown Non-inverting differential LVPECL clock input.
3
nPCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
4
PCLK1
Input
Pulldown Non-inverting differential clock input.
5
nPCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
6
PCLK2
Input
Pulldown Non-inverting differential clock input.
7
nPCLK2
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
8
PCLK3
Input
Pulldown Non-inverting differential clock input.
9
nPCLK3
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
10
OE
Input
Pullup Output enable pin. See Table 4B. LVCMOS/LVTTL interface levels.
11
SEL_OUT Input
Pullup
Output select pin. When LOW, selects LVDS levels. When HIGH, selects LVPECL
levels. LVCMOS/LVTTL interface levels. See Table 3B.
12
13, 18
14, 15
V_{CC_TAP}
V_EE
nQ1, Q1
Power
Power
Output
Positive supply pin. See Table 3A.
Negative supply pins.
Differential output pair. LVPECL or LVDS interface levels.
16, 17
nQ0, Q0 Output
Differential output pair. LVPECL or LVDS interface levels.
19
V_CC
Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
R_PULLUP
R_PULLDOWN
R_VCC/2
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Input Pullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
75
Maximum
Units
pF
k
k
k
ICS859S0412BGI REVISION A MAY 23, 2012
2
©2012 Integrated Device Technology, Inc.