ICS859S0412I Datasheet, PDF (1/23 Pages) Integrated Device Technology – Maximum output frequency

4:2, Differential-to-LVPECL/LVDS
Clock Multiplexer
ICS859S0412I
DATA SHEET
General Description
The ICS859S0412I is a 4:2 Differential-to-LVPECL/ LVDS Clock
Multiplexer which can operate up to 3GHz. The ICS859S0412I has 4
selectable differential PCLKx/nPCLKx clock inputs. The PCLKx,
nPCLKx input pairs can accept LVPECL, LVDS, CML or levels. The
fully differential architecture and low propagation delay make it ideal
for use in clock distribution circuits.
Features
• High speed 4:1 differential multiplexer with a 1:2 fanout buffer
• Two differential LVPECL or LVDS output pairs
• Four selectable differential PCLKx, nPCLKx input pairs
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
• Maximum output frequency: 3GHz
• Translates any single ended input signal to LVPECL levels with
resistor bias on nPCLKx input
• Part-to-part skew: 100ps (maximum)
• Propagation delay: 565ps (typical) at 3.3V
• Additive phase jitter, RMS: 0.22ps (typical) at 3.3V
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
OE ^Pullup
CLK_SEL0 ^Pulldown
CLK_SEL1 ^Pulldown
PCLK0 ^Pulldown
nPCLK0 ^{Pullup/Pulldown}
PCLK1 ^Pulldown
nPCLK1 ^{Pullup/Pulldown}
PCLK2 ^Pulldown
nPCLK2 ^{Pullup/Pulldown}
PCLK3 ^Pulldown
nPCLK3 ^{Pullup/Pulldown}
SEL_OUT ^Pullup
00
01
10
11
Q0
nQ0
Q1
nQ1
ICS859S0412BGI REVISION A MAY 23, 2012
Pin Assignment
CLK_SEL1 1
PCLK0 2
20 CLK_SEL0
19 VCC
nPCLK0 3
PCLK1 4
18 VEE
17 Q0
nPCLK1 5
PCLK2 6
nPCLK2 7
PCLK3 8
nPCLK3 9
OE 10
16 nQ0
15 Q1
14 nQ1
13 VEE
12 VCC_TAP
11 SEL_OUT
ICS859S0412I
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
1
©2012 Integrated Device Technology, Inc.