ICS859S0212I Datasheet, PDF (2/23 Pages) Integrated Device Technology – Propagation delay

ICS859S0212I Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
CLK_SEL
Input
Pulldown Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
2
PCLK0
Input
Pulldown Non-inverting differential LVPECL clock input.
3
nPCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
4
PCLK1
Input
Pulldown Non-inverting differential clock input.
5
nPCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
6
nc
Unused
No connect.
7
OE
Input
Pullup Output enable pin. See Table 4B. LVCMOS/LVTTL interface levels.
8
SEL_OUT
Input
Pullup
Output select pin. When LOW, selects LVDS levels. When HIGH, selects LVPECL
levels. LVCMOS/LVTTL interface levels. See Table 3B.
9
10, 15
11, 12
V_{CC_TAP}
V_EE
nQ1, Q1
Power
Power
Output
Positive supply pin. See Table 3A.
Negative supply pins.
Differential output pair. LVPECL or LVDS interface levels.
13, 14
nQ0, Q0
Output
Differential output pair. LVPECL or LVDS interface levels.
16
V_CC
Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
R_PULLDOWN
R_VCC/2
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
75
Maximum
Units
pF
k
k
k
ICS859S0212BGI REVISION A JUNE 4, 2012
2
©2012 Integrated Device Technology, Inc.