ICS859S0212I Datasheet, PDF (16/23 Pages) Integrated Device Technology – Propagation delay

ICS859S0212I Data Sheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (Z_T) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z₀) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
standard termination schematic as shown in Figure 4A can be used
with either type of output structure. Figure 4B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS
Driver
Z_O  Z_T
Figure 4A. Standard Termination
LVDS
Z_T
Receiver
LVDS
Driver
Z_O  Z_T
Figure 4B. Optional Termination
Z_T
2 _LVDS
C
Z_T Receiver
2
LVDS Termination
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are a low impedance follower output that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
Z_o = 50Ω
3.3V
+
LVPECL
Z_o = 50Ω
R1
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
* Z_o
_
Input
R2
50Ω
V_CC - 2V
RTT
Figure 5A. 3.3V LVPECL Output Termination
ICS859S0212BGI REVISION A JUNE 4, 2012
3.3V
LVPECL
3.3V
R3
R4
125Ω
125Ω
3.3V
Z_o = 50Ω
+
Z_o = 50Ω
R1
84Ω
_
R2
84Ω
Input
Figure 5B. 3.3V LVPECL Output Termination
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©2012 Integrated Device Technology, Inc.