ICS854S058I Datasheet, PDF (2/16 Pages) Integrated Device Technology – One differential LVDS output pair

ICS854S058I Datasheet
8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 20
6, 7, 8
9
10
11
12
13
14
15
16
17
18, 19
21
22
23
24
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V_DD
SEL0,
SEL1,
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
nPCLK4
PCLK4
nPCLK5
PCLK5
GND
nQ, Q
nPCLK6
PCLK6
nPCLK7
PCLK7
Input
Input
Input
Input
Power
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Input
Pulldown
Input
Input
Input
Input
Input
Input
Input
Input
Power
Output
Input
Input
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Description
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_DD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_DD/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_DD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_DD/2 default when left floating.
Inverting differential LVPECL clock input. V_DD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_DD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Power supply ground.
Differential output pair. LVDS interface levels.
Inverting differential LVPECL clock input. V_DD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_DD/2 default when left floating.
Non-inverting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLDOWN
R_VDD/2
Parameter
Input Capacitance
Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
75
50
Maximum
Units
pF
k
k
ICS854S058AGI REVISION A OCTOBER 29, 2012
2
©2012 Integrated Device Technology, Inc.