ICS854S058I Datasheet, PDF (11/16 Pages) Integrated Device Technology – One differential LVDS output pair

ICS854S058I Datasheet
8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Schematic Example
An application schematic example of ICS854S058I is shown in
Figure 4. The inputs can accept various types of differential signals.
In this example, the inputs are driven by LVDS drivers. The
transmission lines are assumed to be 100 differential. The 100
matched loads termination should be located near the receivers. It is
recommended at least one decoupling capacitor per power pin. The
decoupling capacitor should be low ESR and located as close as
possible to the power pin.
Zo = 50
LVDS
Zo = 50
100 Ohm Differential
VDD=3.3V
100 Ohm Differential
Zo = 50
VDD
R2
100
Zo = 50
LVDS
C1
0.1u
U1
1
2 ^PCLK0
3 ^nPCLK0
4 ^PCLK1
5 ^nPCLK1
6 ^VDD
7 ^SEL0
8 ^SEL1
9 ^SEL2
10 ^PCLK2
11 ^nPCLK2
12 ^PCLK3
nPCLK3
ICS854S058
Figure 4. ICS854S058I Schematic Example
Logic Control Input Examples
Set Logic
Set Logic
R1
VDD _{Input to '1'} VDD _{Input to '0'}
100
RU1
1K
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
24
PCLK7 ₂₃
nPCLK7 ₂₂
PCLK6 ₂₁
nPCLK6 ₂₀
VDD ₁₉
Q ₁₈
nQ ₁₇
GND ₁₆
PCLK5 ₁₅
nPCLK5 ₁₄
PCLK4 ₁₃
nPCLK4
VDD
Zo = 50
R3
100
Zo = 50
C2
0.1u
100 Ohm Differential
+
-
LVDS
ICS854S058AGI REVISION A OCTOBER 29, 2012
11
©2012 Integrated Device Technology, Inc.