ICS844008I Datasheet, PDF (2/18 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

ICS844008I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 2 QA0, nQA0 Output
Differential output pair. LVDS interface levels.
3, 12,
22, 27
4, 5
6, 13,
19, 29
7, 8
V_DD
QA1, nQA1
Power
Ouput
GND
Power
QA2, nQA2 Output
Core supply pins.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
9
F_SEL
Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
10, 11 QA3, nQA3 Output
Differential output pair. LVDS interface levels.
14, 15
16
17, 18
QB0, nQB0
MR
nQB1, QB1
Output
Input
Output
Pulldown
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs to go low and the inverted output to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
20, 21 nQB2, QB2 Output
Differential output pair. LVDS interface levels.
23, 24 nQB3, QB3 Output
Differential output pair. LVDS interface levels.
25
V_DDA
Power
Analog supply pin.
Selects between the PLL and XTAL as input to the dividers. When LOW,
26
nPLL_SEL Input Pulldown selects PLL (PLL enabled). When HIGH, selects the XTAL (PLL bypassed).
LVCMOS/LVTTL interface levels.
28
OEB
Input
Pullup
Output enable for QB[0:3]/nQB[0:3] outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
30, 31
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
32
OEA
Input
Pullup
Output enable for QA[0:3]/nQA[0:3] outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R
PULLDOWN
R_PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3A. OEA FUNCTION TABLE
Input
OEA
0
1
Outputs
QA[0:3], nQA[0:3]
High Impedance state
Normal operation
TABLE 3B. OEB FUNCTION TABLE
Input
OEB
0
1
Outputs
QB[0:3], nQB[0:3]
High Impedance state
Normal operation
IDT^™ / ICS^™ LVDS FREQUENCY SYNTHESIZER
2
ICS844008AYI-01 REV. B NOVEMBER 21, 2008