ICS844008I Datasheet, PDF (11/18 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

ICS844008I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
SCHEMATIC LAYOUT
Figure 7 shows an example of ICS844008I-01 application
schematic. In this example, the device is operated at V = 3.3V.
DD
The 18pF parallel resonant 25MHz crystal is used. The C1 =
27pF and C2 = 27pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 may be slightly
adjusted for optimizing frequency accuracy. Two examples of
LVDS for receiver without built-in termination are shown in this
schematic.
VDD
OEB
C5
0.1uF
VDDA
VDD
C1
27pF
X1
25M₁ H_{8 p} z_F
C2
27pF
VDD
C7
0.1uF
QA0
nQA0
QA1
nQA1
QA2
nQA2
OEA
U1
1
2 ^QA0
3 ^nQA0
4
5
6
7
8
VDD
QA1
nQA1
GND
QA2
nQA2
nPLL_SEL
C3
0.01u
C4
10uF
R1
10
Q7
Zo = 50 Ohm
+
R2
Zo = 50 Ohm
100
nQ7
-
24
QB3 ₂₃
nQB3 ₂₂
VDD
QB2
nQB2
GND
QB1
nQB1
21
20
19
18
17
QB3
nQB3
QB2
nQB2
QB1
nQB1
VDD
C6
0.1uF
VDD=3.3V
I C S844008I -01
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
F_SEL
MR
VDD
C8
0.1uF
Zo = 50 Ohm
Q5
R3
50
+
C9
0.1uF
-
R4
Zo = 50 Ohm
50
nQ5
Alternate
LVDS
Termination
FIGURE 7. ICS844008I-01 SCHEMATIC LAYOUT
IDT^™ / ICS^™ LVDS FREQUENCY SYNTHESIZER
11
ICS844008AYI-01 REV. B NOVEMBER 21, 2008