ICS831721I Datasheet, PDF (2/17 Pages) Integrated Device Technology – Differential Clock/Data Multiplexer

ICS831721I Data Sheet
DIFFERENTIAL CLOCK/DATA MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3, 8, 11, 14
4
5
6, 10
7
Name
CLK0
nCLK0
V_DD
CLK1
nCLK1
GND
nc
Input
Input
Power
Input
Input
Power
Unused
Type
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Description
Non-inverting clock/data input 0.
Inverting differential clock input 0. V_DD/2 default when left floating.
Positive power supply.
Non-inverting clock/data input 1.
Inverting differential clock input 1. V_DD/2 default when left floating.
Power supply ground.
No connect.
9
nOE
Input
Pullup
Output enable. See Table 3A for function. LVCMOS/LVTTL interface levels.
12, 13
15
16
Q, nQ
SEL
IREF
Output
Input
Input
Pulldown
Differential output pair. HCSL interface levels.
Input select. See Table 3B for function. LVCMOS/LVTTL interface levels.
An external fixed precision resistor (475Ω) from this pin to ground provides
a reference current used for the differential current-mode Q, nQ outputs.
NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
R_PULLDOWN
R_PULLUP
Input Capacitance
Input Pulldown Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
Function Tables
Table 3A. nOE Configuration Table
Input
nOE
Operation
0
Output Q, nQ is enabled.
1 (default)
Output Q, nQ is in a high-impedance state.
NOTE: nOE is an asynchronous control.
Table 3B. SEL Configuration Table
Input
SEL
Selected Input
0 (default)
CLK0, nCLK0
1
CLK1, nCLK1
NOTE: SEL is an asynchronous control.
ICS831721AGI REVISION A AUGUST 19, 2011
2
©2011 Integrated Device Technology, Inc.