843003AGLF Datasheet, PDF (2/21 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS843003
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 6
7
8
9
10
11
12
13
14
15,
16
17
18
19, 20
21, 22
23
24
Name
DIV_SELB0
VCO_SEL
MR
V_{CCO_A}
QA0, nQA0
OEB
OEA
FB_DIV
V_CCA
V_CC
DIV_SELA0
DIV_SELA1
V_EE
XTAL_OUT,
XTAL_IN
TEST_CLK
XTAL_SEL
nQB1, QB1
nQB01, QB0
V_{CCO_B}
DIV_SELB1
Type
Input Pulldown
Input
Pullup
Input Pulldown
Power
Output
Input
Pullup
Input
Pullup
Input
Power
Power
Input
Input
Power
Pulldown
Pullup
Pulldown
Input
Input Pulldown
Input
Pullup
Output
Output
Power
Input
Pullup
Description
Division select pin for Bank B. Default = Low. LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
TEST_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Has an internal
pulldown resistor so the power-up default state of outputs and dividers are enabled.
LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVPECL interface levels.
Output enable Bank B. Active High output enable. When logic HIGH, the output pair
on Bank B is enabled. When logic LOW, the output pair drives differential Low
(QB0 = Low, nQB0 = High). Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH, the 2 output
pairs on Bank A are enabled. When logic LOW, the output pair drives differential
Low (QA0 = Low, nQA0 = High). Has an internal pullup resistor so the default
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set for ÷20.
When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels.
Division select pin for Bank A. Default = Low. LVCMOS/LVTTL interface levels.
Negative supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a
single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to pull to low
state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pin for Bank B outputs.
Division select pin for Bank B. Default = High. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
2
ICS843003AG REV. A OCTOBER 23, 2008