843003AGLF Datasheet, PDF (15/21 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS843003
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Layout Guideline
Figure 6A shows a schematic example of the ICS843003. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18 pF
parallel resonant 31.25MHz crystal is used. The C1= 27pF and
C2 = 33pF are recommended for frequency accuracy. The C1 and
C2 may be slightly adjusted for optimizing frequency accuracy.
VCC
R2
10 C3
10uF
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
VCCA
C4
0.01u
VCC
C6
0.1u
U1
ICS843003
C2
33pF
X1
31.25₁M₈ H_p z_F
C1
27pF
VCCO
C7
0.1u
3.3V
R3
133
Zo = 50 Ohm
Zo = 50 Ohm
R4
82.5
R5
133
+
-
R6
82.5
VCC=3.3V
3.3V
VCCO=3.3V
R7
R9
133
133
Zo = 50 Ohm
+
Zo = 50 Ohm
-
C8
0.1u
R8
82.5
R10
82.5
Figure 6A. ICS843003 Schematic Example
PC Board Layout Example
Figure 5B shows an example of ICS843003 P.C. board layout. The
crystal X1 footprint shown in this example allows installation of
either surface mount HC49S or through-hole HC49 package. The
footprints of other components in this example are listed in the
Figure 6B. ICS843003 PC Board Layout Example
Table 7. There should be at least one decoupling capacitor per
power pin. The decoupling capacitors should be located as close
as possible to the power pins. The layout assumes that the board
has clean analog power ground plane.
Table 7. Footprint Table
Reference
Size
C1, C2
0402
C3
0805
C4, C5, C6, C7, C8
0603
R2
0603
NOTE: Table 7, lists component sizes shown in this layout
example.
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
15
ICS843003AG REV. A OCTOBER 23, 2008