IDT71P71804 Datasheet, PDF (19/23 Pages) Integrated Device Technology – 18Mb Pipelined DDR™II SRAM Burst of 2

IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
JTAG DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit Note
Commercial Temperature Range
I/O Power Supply
VDDQ
1.4
-
VDD
V
Power Supply Voltage
VDD
1.7
1.8
1.9
V
Input High Level
VIH
1.3
- VDD+0.3 V
Input Low Level
VIL
-0.3
-
0.5
V
TCK Input Leakage Current
IIL
-5
-
+5
µA
TMS, TDI Input Leakage Current
IIL
-15
-
+15
µA
TDO Output Leakage Current
IOL
-5
-
+5
µA
Output High Voltage (IOH = -1mA) VOH
VDDQ - 0.2
-
VDDQ
V
1
Output Low Voltage (IOL = 1mA)
VOL
VSS
-
0.2
V
1
NOTE:
6112 tbl 19
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.
JTAG AC Test Conditions
Parameter
Symbol Min
Input High Level
VIH
1.8
Input Low Level
VIL
0
Input Rise/Fall Time
TR/TF 1.0/1.0
Input and Output Timing Reference Level
0.9
NOTE:
1. For SRAM outputs see AC test load on page 12.
Unit Note
V
V
ns
V
1
6112 tbl 20
JTAG Input Test Waveform
1.8 V
0V
0.9 V
Test points
0.9 V
6112 drw 23
JTAG Output Test Waveform
0.9 V
Test points
0.9 V
6112 drw 24
JTAG AC Test Load
0.9 V
TDO
Z0 = 50Ω
50Ω
,
6112 drw 25
61.492