IDT71P71804 Datasheet, PDF (1/23 Pages) Integrated Device Technology – 18Mb Pipelined DDR™II SRAM Burst of 2

18Mb Pipelined
DDR™II SRAM
Burst of 2
IDT71P71804
IDT71P71604
Features
◆ 18Mb Density (1Mx18, 512kx36)
◆ Common Read and Write Data Port
◆ Dual Echo Clock Output
◆ 2-Word Burst on all SRAM accesses
◆ Multiplexed Address Bus
- One Read or One Write request per clock cycle
◆ DDR (Double Data Rate) Data Bus
- Two word bursts data per clock
◆ Depth expansion through Control Logic
◆ HSTL (1.5V) inputs that can be scaled to receive signals from
1.4V to 1.9V.
◆ Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70
ohms
◆ 1.8V Core Voltage (VDD)
◆ 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Description
The IDT DDRII^TM Burst of two SRAMs are high-speed synchro-
nous memories with a double-data-rate (DDR), bidirectional data port.
This scheme allows maximization of the bandwidth on the data bus by
passing two data items per clock cycle. The address bus operates at
single data rate speeds, allowing the user to fan out addresses and
ease system design while maintaining maximum performance on data
transfers.
The DDRII has scalable output impedance on its data output bus
and echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds
beyond SRAM devices that use any form of TTL interface. The inter-
face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
Clocking
The DDRII SRAM has two sets of input clocks, namely the K, K
clocks and the C, C clocks. In addition, the DDRII has an output “echo”
clock, CQ, CQ.
Functional Block Diagram
DATA
REG
(Note2)
SA
SA0
ADD
REG
(Note2)
LD
R/W
BW x
(Note3)
CTRL
LOGIC
(Note 1)
WRITE DRIVER
18M
MEMORY
ARRAY
(Note1)
(Note4)
(Note1) _DQ
K
CLK
K
GEN
C
SELECT OUTPUT CONTROL
C
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x18 and 19 address signal lines for x36.
3) Represents 2 signal lines for x18 and 4 signal lines for x36.
4) Represents 36 signal lines for x18 and 72 signal lines for x36.
6112 drw 16
CQ
CQ
APRIL 2006
1
©2006 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
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