ICS853S012I Datasheet, PDF (16/22 Pages) Integrated Device Technology – Maximum output frequency

ICS853S012I Data Sheet
12-:1, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL CLOCK/DATA MULTIPLEXER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853S031I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853S031I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.465V * 70mA = 242.55mW
• Power (outputs)_MAX = 31.12mW/Loaded Output pair
Total Power__MAX (3.465V, with all outputs switching) = 242.55mW + 31.12mW = 273.67mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming a moderate air
flow of 1 meter per second and a multi-layer board, the appropriate value is 39.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.274W * 39.5°C/W = 95.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance _JA for 32 Lead VFQFN, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
39.5°C/W
1
34.5°C/W
2.5
31.0°C/W
ICS853S0121AKI REVISION A SEPTEMBER 28, 2012
16
©2012 Integrated Device Technology, Inc.