ICS853S012I Datasheet, PDF (1/22 Pages) Integrated Device Technology – Maximum output frequency

12:1, Differential-to-3.3V, 2.5V
LVPECL Clock/Data Multiplexer
ICS853S012I
DATA SHEET
General Description
The ICS853S012I is an 12:1 Differential-to-3.3V or 2.5V LVPECL
Clock/Data Multiplexer which can operate up to 3.2GHz. The
ICS853S012I has twelve differential selectable clock inputs. The
CLK, nCLK input pairs can accept LVPECL, LVDS or CML levels.
The fully differential architecture and low propagation delay make it
ideal for use in clock distribution circuits. The select pins have
internal pulldown resistors.
Features
• High speed 12:1 differential multiplexer
• One differential 3.3V or 2.5V LVPECL output
• Twelve selectable differential clock or data inputs
• CLKx, nCLKx pairs can accept the following differential input
levels: LVPECL, LVDS, CML
• Maximum output frequency: 3.2GHz
• Translates any single ended input signal to LVPECL levels with
resistor bias on nCLKx input
• Additive phase jitter, RMS: 0.144ps (typical)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.15ns (maximum)
• Full 3.3V or 2.5V operating supply modes
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package
Block Diagram
CLK0 ^Pulldown
nCLK0 ^{Pullup/Pulldown}
CLK1 Pulldown
nCLK1 ^{Pullup/Pulldown}
CLK2 ^Pulldown
nCLK2 ^{Pullup/Pulldown}
Q
nQ
CLK11 ^Pulldown
nCLK11 ^{Pullup/Pulldown}
SEL[3:0]
ICS853S0121AKI REVISION A SEPTEMBER 28, 2012
Pin Assignment
32 31 30 29 28 27 26 25
CLK2 1
24 CLK9
nCLK2 2
23 nCLK9
VCC 3
22 SEL0
Q4
21 SEL1
nQ 5
20 SEL2
VEE 6
19 SEL3
CLK3 7
18 CLK8
nCLK3 8
17 nCLK8
9 10 11 12 13 14 15 16
ICS853S012I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
1
©2012 Integrated Device Technology, Inc.