ICS853S012I Datasheet, PDF (11/22 Pages) Integrated Device Technology – Maximum output frequency

ICS853S012I Data Sheet
12-:1, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL CLOCK/DATA MULTIPLEXER
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, CML and other differential
signals. Both V_SWING and V_OH must meet the V_PP and V_CMR input
requirements. Figures 2A to 2E show interface examples for the
IN/nIN input with built-in 50 terminations driven by the most
common driver types. The input interfaces suggested here are
examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
CLK
nCLK
Differential
R1
R2
84Ω
84Ω
Input
Figure 2A. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
R2
50Ω
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
3.3V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
Differential
Input
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVDS Driver
Figure 2D. CLK/nCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50
50
3.3V
CLK
nCLK
Differential
Input
Figure 2E. CLK/nCLK Input Driven by an
IDT Open Collector CML Driver
ICS853S0121AKI REVISION A SEPTEMBER 28, 2012
11
©2012 Integrated Device Technology, Inc.