83905-01 Datasheet, PDF (15/20 Pages) Integrated Device Technology – Outputs able to drive 12 series terminated lines

83905-01 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 83905-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 83905-01 is the sum of the core power plus the analog power plus the power dissipated due to the load. The
following is the power dissipation for V_DD = 1.8V + 0.2V = 2.0V, which gives worst case results.
• Power (core)_MAX = V_{DD_MAX} * I_DD = 2V * 10mA = 20mW
• Output Impedance R_OUT Power Dissipation due to Loading 50 to V_DD/2
Output Current I_OUT = V_{DD_MAX} / [2 * (50 + R_OUT)] = 2V / [2 * (50 + 17)] = 14.9mA
• Power Dissipation on the R_OUT per LVCMOS output
Power (R_OUT) = R_OUT * (I_OUT)² = 17 * (14.9mA)² = 3.8mW per output
• Total Power Dissipation on the R_OUT
Total Power (R_OUT) = 3.8mW * 6 = 22.8mW
Dynamic Power Dissipation at 100MHz
Power (100MHz) = C_PD * Frequency * (V_DD)² = 12pF * 100MHz * (2V)² = 4.8mW per output
Total Power (100MHz) = 4.8mW * 6 = 28.8mW
Total Power Dissipation
• Total Power
= Power (core)_MAX + Total Power (R_OUT) + Total Power (100MHz)
= 20mW + 22.8mW + 28.8mW
= 71.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 100.3°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.072W *100.3°C/W = 77.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance _JA for 16-Lead TSSOP, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
100.3°C/W
1
96.0°C/W
2.5
93.9°C/W
REVISION 1 05/01/15
15
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER