83905-01 Datasheet, PDF (14/20 Pages) Integrated Device Technology – Outputs able to drive 12 series terminated lines

83905-01 DATA SHEET
Schematic Example
Figure 4 shows an example of the 83905-01 application schematic.
In this example, the device is operated at V_DD = V_DDO = 1.8V. The
decoupling capacitors should be located as close as possible to the
power pin. The input is driven by an 18pF load resonant quartz
crystal. The tuning capacitors C1 and C2 are fairly accurate, but
minor adjustments might be required. For the LVCMOS output
drivers, two termination examples are shown in this schematic. For
additional termination examples, see LVCMOS Termination
Application Note.
CL = 18 pf
VD DO = 1.8V
VDD = 1. 8V
R2
31 Z o = 50 Ohm
C2
15pf
EN ABLE 2
VDD O
U1
1
2 ^XTAL_OUT
3 ^{EN ABLE 2}
4 GND
5 ^{BC LK0}
6 VD DO
7 ^{BC LK1}
8 ^GND
BC LK2
C1
15pF
16
XTAL_IN ₁₅
EN ABLE 1 ₁₄
BCLK5 13
VD DO ₁₂
BCLK4 11
G ND ₁₀
BCLK3 ₉
VDD
ENABLE 1
LVCMO S
VDD
R3
100
Z o = 50 Ohm
R4
100
LVCMO S
VDD
C3
10uF
C4
.1uF
VDD O
C5
. 1uF
C6
.1uF
Optional Termination
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
Figure 4. 83905-01 Schematic Layout
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER
14
REVISION 1 05/01/15