ICS87973I-147 Datasheet, PDF (14/19 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Schmatic Example
Figure 6 shows a schematic example of using ICS87973I-147. This
example shows general design of input, output termination, logic
control input pull up/down and power supply filtering. In this
example, the clock input is driven by an LVCMOS driver.
R1
43
Zo = 50
VDD
U1
VDD
R9 1K
Serial Clcok
R8
1K
VDD
R10 1K
Serial Data
RS
Zo = 50
LVCMOS CLOCK
R7
VDD
1
2
3
4
5
6
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2
7
8
9
10
PLL_SEL
REF_SEL
CLK_SEL
CLK0
11
12
13
CLK1
CLK
nCLK
VDDA
39
GNDO
QB0
VDDO
QB1
GNDO
38
37
36
35
34
QB2
VDDO
QB3
EXT_FB
33
32
31
30
GNDO
QFB
VDD
FSEL_FB0
29
28
27
10 - 15
C16
10u
C11
0.01u
R5
R6
1K
1K
ICS87973I-147
R2 43
Zo = 50
Logic Input Pin Examples
R4
1K
Set Logic
Set Logic
VDD _{Input to} VDD _{Input to}
'1'
'0'
RU1
1K
RU2
Not Install
R3 43
Zo = 50
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
(U1-17)
(U1-22) (U1-28) (U1-33) (U1-37) (U1-45) (U1-49)
VDD
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
VDD=3.3V
ICS87973I-147 Schematic Layout
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
14
ICS87973DYI-147 REV. A DECEMBER 9, 2008