ICS87973I-147 Datasheet, PDF (12/19 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V_PP and
V_CMR input requirements. Figures 4A to 4E show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 4A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
3.3V
R1
R2
50
50
CLK
nCLK
HiPerClockS
Input
Figure 4A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50
50
nCLK
HiPerClockS
Input
R2
50
Figure 4B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
CLK
nCLK
HiPerClockS
R1
R2
84
84
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
Receiver
Figure 4C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
*R3 33
Zo = 50Ω
Zo = 50Ω
*R4 33
HCSL
R1
50
*Optional – R3 and R4 can be 0Ω
3.3V
CLK
nCLK
HiPerClockS
R2
Input
50
Figure 4E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 4D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
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ICS87973DYI-147 REV. A DECEMBER 9, 2008