844003 Datasheet, PDF (14/18 Pages) Integrated Device Technology – FemtoClock Crystal-to-3.3V LVDS Frequency Synthesizer

844003 Datasheet
Logic Control Input Examples
Set Logic
Set Logic
VD D _{Input to '1'} VDD _{Input to '0'}
R U1
1K
To Logic
Input
pins
R D1
N ot I nst all
RU 2
Not Install
To Logic
Input
pins
RD 2
1K
VDD
C8
10uF
3.3V
FB1
2
1
B LM18B B221S N1
C7
0.1uF
C10
0.1uF
Place each 0.1uF bypass cap directly
adjacent to its respective VDD or
VDDA pin.
10 R6
VDD A
3. 3V
Ro
= 7 Oh m
OEA
OEB
MR
VCO _SEL
F B_D IV
XTAL_S E L
DI V_SELA0
DI V_SELA1
DI V_SELB0
DI V_SELB1
R7
43
LVCMOS_Dr iv er
Zo = 50 Ohm
U1
8
7 ^OEA
OEB
4
VDD O_A
3
2 ^MR
VC O_SEL
9
23
18 ^{F B_DIV VDD O_B}
XTA L_SE L
12
13 D IV_SELA0
D IV_SELA1
1
24 D IV_SELB0
D IV_SELB1
5
QA 0
6
nQA 0
C12
0. 1uF
C 21
0. 1uF
C 16
0. 1uF
QA0
nQ A0
C9
10uF
3.3V
FB2
2
1
C11
10uF
BLM18BB221SN 1
C13
0. 1uF
Place each 0.1uF bypass cap directly
adjacent to the corresponding VDDO_x
pi n.
Zo = 50 Ohm
+
R1
100
Zo = 50 Ohm
-
17
TEST_C LK
22
QB 0
21
nQB 0
QB0
nQ B0
LVDS R eceiver
LVDS Termination
15
XTAL_OU T
31. 25 MH z (18pf )
X1
16
XTA L_IN
20
QB 1
19
nQB 1
QB1
nQ B1
C1 Z o = 50 Ohm
0.1u
VD D_Rx
C5
C4
22pF
22pF
R2
R4
50
+
Figure 3. 844003 Application Schematic
C3
R5
0.01uF
-
R3
50
Rec ei v er
C2 Z o = 50 Ohm
0.1u
Alternate AC coupled LVDS Termination
(Select R4 and R5 t o center the LVDS swing in the
common mode center of the Receiver.)
©2016 Integrated Device Technology, Inc.
14
January 29, 2016