844003 Datasheet, PDF (12/18 Pages) Integrated Device Technology – FemtoClock Crystal-to-3.3V LVDS Frequency Synthesizer

844003 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termi-
nation impedance (Z_T) is between 90 and 132. The actual value
should be selected to match the differential impedance (Z₀) of your
transmission line. A typical point-to-point LVDS design uses a 100
parallel resistor at the receiver and a 100 differential transmis-
sion-line environment. In order to avoid any transmission-line reflec-
tion issues, the components should be surface mounted and must be
placed as close to the receiver as possible. IDT offers a full line of
LVDS compliant devices with two types of output structures: current
source and voltage source. The standard termination schematic as
shown in Figure 2A can be used with either type of output structure.
Figure 2B, which can also be used with both output types, is an op-
tional termination with center tap capacitance to help filter common
mode noise. The capacitor value should be approximately 50pF. If us-
ing a non-standard termination, it is recommended to contact IDT
and confirm if the output structure is current source or voltage source
type. In addition, since these outputs are LVDS compatible, the input
receiver’s amplitude and common-mode input range should be veri-
fied for compatibility with the output.
LVDS
Driver
Z_O  Z_T
Figure 2A. Standard Termination
LVDS
Z_T
Receiver
LVDS
Driver
Z_O  Z_T
Figure 2B. Optional Termination
LVDS Termination
Z_T
2 _LVDS
C
Z_T Receiver
2
©2016 Integrated Device Technology, Inc.
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January 29, 2016