844003 Datasheet, PDF (13/18 Pages) Integrated Device Technology – FemtoClock Crystal-to-3.3V LVDS Frequency Synthesizer

844003 Datasheet
Schematic Layout
Figure 3 shows an example 844003 application schematic. The sche-
matic example focuses on functional connections and is not configu-
ration specific with the exception of the selection of the 31.25MHz
crystal frequency. This decision requires that FB_DIV = 0. If a
26.041666MHz crystal had been selected, then FB_DIV = 1. Refer to
the pin description and functional tables in the datasheet to ensure
the logic control inputs are properly set. Input and output terminations
shown are intended as examples only and may not represent the ex-
act user configuration.
In this example an 18pF parallel resonant 31.25MHz crystal is used
with load caps C4 = C5 = 22pF. The load caps shown were used to
tune the IDT device characterization board and are recommended for
frequency accuracy, but these may be adjusted for different board
layouts. Crystals with different load capacities may be used, but the
load capacitors will have to be changed accordingly. If different crys-
tal types are used, please consult IDT for recommendations.
The schematic example shows two different LVDS output termina-
tions; the standard termination 100 shunt termination for an LVDS
compliant receiver and an ac coupled termination for a non- LVDS dif-
ferential receiver. The ac coupled termination requires that the de-
signer select the values of R4 and R5 in order to center the LVDS
swing within the common mode range of the receiver. In addition the
designer must make sure that the target receiver will operate reliably
with the LVDS swing, which is reduced relative to other logic families
such as HCSL or LVPECL.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 844003 provides separate
V_DD, V_DDA, V_{DDO_A} and V_{DDO_B} pins to isolate any high speed
switching noise at the outputs from coupling into the internal PLL.
In order to achieve the best possible filtering, it is highly recommend-
ed that the 0.1µF capacitors be placed on the 844003 side of the PCB
as close to the power pins as possible. This is represented by the
placement of these capacitors in the schematic. If space is limited,
the ferrite beads, 10uf capacitors and the 0.1uF capacitors connect-
ed directly to 3.3V can be placed on the opposite side of the PCB. If
space permits, place all filter components on the device side of the
board.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component val-
ues be adjusted and if required, additional filtering be added. Addi-
tionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all de-
vices.
©2016 Integrated Device Technology, Inc.
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January 29, 2016