ICS85105I Datasheet, PDF (12/16 Pages) Integrated Device Technology – LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

ICS85105I
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85105I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85105I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 10% = 3.63V, which gives worst case results.
DD
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core) = V * I = 3.63V * 27mA = 98.01mW
MAX
DD_MAX
DD_MAX
• Power (outputs) = 47.3mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 5 * 47.3mW = 236.5mW
Total Power (3.63V, with all outputs switching) = 98.01mW + 236.5mW = 334.51mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming no air
JA
flow and a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.335W * 91.1°C/W = 115.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 20-LEADN TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
Multi-Layer PCB, JEDEC Standard Test Boards
91.1°C/W
86.7°C/W
2.5
84.6°C/W
IDT^™ / ICS^™ 0.7V HCSL FANOUT BUFFER
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ICS85105AGI REV. A JUNE 5, 2008