ICS85105I Datasheet, PDF (10/16 Pages) Integrated Device Technology – LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

ICS85105I
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
PP
and V_CMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V
CLK
nCLK _HiPerClockS
Input
R1
R2
50
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
HIPERCLOCKS LVHSTL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3
R4
125
125
3.3V
CLK
nCLK _HiPerClockS
Input
R1
R2
84
84
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
CLK
nCLK _HiPerClockS
Input
R1
R2
50
50
R3
50
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
3.3V
Zo = 50 Ohm
LVDS_Driv er
R1
100
Zo = 50 Ohm
3.3V
CLK
nCLK _{Receiv er}
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
2.5V
*R3 33
Zo = 50Ω
Zo = 50Ω
*R4 33
HCSL
R1
50
*Optional – R3 and R4 can be 0Ω
3.3V
CLK
nCLK
HiPerClockS
R2
Input
50
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
CLK
R1
R2
120
120
nCLK
HiPerClockS
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
IDT^™ / ICS^™ 0.7V HCSL FANOUT BUFFER
10
ICS85105AGI REV. A JUNE 5, 2008