ICS8741004I Datasheet, PDF (11/20 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

ICS8741004I
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
PRELIMINARY
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
LVDS Driver
3.3V
50Ω
+
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
11
ICS8741004BGI REV. B SEPTEMBER 27, 2007