ICS8741004I Datasheet, PDF (1/20 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

PRELIMINARY
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL
PCI EXPRESS™ JITTER ATTENUATOR
ICS8741004I
General Description
The ICS8741004I is a high performance
ICS
Differential-to-LVDS/0.7V Differential Jitter
HiPerClockS™ _{Attenuator designed for use in PCI Express™}
systems. In some PCI Express systems, such as
those found in desktop PCs, the PCI Express clocks
are generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator may be
required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The ICS8741004I has 3 PLL bandwidth modes: 200kHz,
600kHz and 2MHz. The 200kHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may be
attenuated. The 600kHz provides an intermediate bandwidth that
can easily track triangular spread profiles, while providing good
jitter attenuation. The 2MHz bandwidth provides the best tracking
skew and will pass most spread profiles, but the jitter attenuation
will not be as good as the lower bandwidth modes. Because some
2.5Gb serdes have x20 multipliers while others have x25
multipliers, the ICS8741004I can be set for 1:1 mode or 5/4
multiplication mode (i.e. 100MHz input/125MHz output) using the
F_SEL pins.
The ICS8741004I uses IDT’s 3^rd Generation FemtoClock™
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI
Express add-in cards.
PLL Bandwidth
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~600kHz (default)
1 = PLL Bandwidth: ~2MHz
Features
• Two LVDS and two 0.7V differential output pairs
Bank A has two LVDS output pairs and
Bank B has two 0.7V differential output pairs
• One differential clock input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 35ps (maximum)
• Full 3.3V operating supply
• Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
nQA1 1
QA1 2
V_DDO 3
QA0 4
nQA0 5
MR 6
BW_SEL 7
nc 8
V_DDA 9
F_SELA 10
V_DD 11
OEA 12
24 nQB1
23 QB1
22 VDDO
21 QB0
20 nQB0
19 IREF
18 F_SELB
17 OEB
16 GND
15 GND
14 nCLK
13 CLK
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
1
ICS8741004BGI REV. B SEPTEMBER 27, 2007