ICS9FG108 Datasheet, PDF (9/13 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
I²C Table: Output Stop Mode Register
Byte 2
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
DIF_7
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
1
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
PWD
0
0
0
0
0
0
0
0
I²C Table: Frequency Select Readback Register
Byte 3
Pin #
Name
Control
Function
Bit 7
27
SEL14M_25M#¹ _{State of pin 27}
(FS3)
Bit 6
6
Bit 5
44
Bit 4
45
Bit 3
26
Bit 2
Bit 1
Bit 0
FS2¹
FS1¹
FS0¹
SPREAD¹
State of pin 6
State of pin 44
State of pin 45
State of pin 26
RESERVED
RESERVED
RESERVED
Type
R
R
R
R
R
R
R
R
0
1
PWD
See Frequency
Selection Table, Page 1
Off
On
RESERVED
RESERVED
RESERVED
Pin 27
Pin 6
Pin 44
Pin 45
Pin 26
X
X
X
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
0823—04/02/04
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