ICS9FG108 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
Pin Description
PIN #
PIN NAME PIN TYPE
DESCRIPTION
1 XIN/CLKIN
IN Crystal input or Reference Clock input
2 X2
OUT Crystal output, Nominally 14.318MHz
3 VDD
PWR Power supply, nominal 3.3V
4 GND
PWR Ground pin.
5 REFOUT
IN Reference Clock output
6 FS2
IN Frequency select pin.
7 OE_7**
IN ^{Active high input for enabling outputs.}
0 = tri-state outputs, 1= enable outputs
8 DIF_7
OUT 0.7V differential true clock outputs
9 DIF_7#
OUT 0.7V differential complement clock outputs
10 VDD
PWR Power supply, nominal 3.3V
11 DIF_6
OUT 0.7V differential true clock outputs
12 DIF_6#
OUT 0.7V differential complement clock outputs
13 OE_6*
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
14 VDD
PWR Power supply, nominal 3.3V
15 GND
PWR Ground pin.
16 OE_5*
Active high input for enabling outputs.
IN _{0 = tri-state outputs, 1= enable outputs}
17 DIF_5
OUT 0.7V differential true clock outputs
18 DIF_5#
OUT 0.7V differential complement clock outputs
19 VDD
PWR Power supply, nominal 3.3V
20 DIF_4
OUT 0.7V differential true clock outputs
21 DIF_4#
OUT 0.7V differential complement clock outputs
22 OE_4**
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
23 SDATA
I/O Data pin for SMBus circuitry, 5V tolerant.
24 SCLK
IN Clock pin of SMBus circuitry, 5V tolerant.
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
0823—04/02/04
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