ICS9FG108 Datasheet, PDF (8/13 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
I²C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Pin #
27
5
44
7
26
Name
Control
Function
FS3¹
FS2¹
FS1¹
FS0¹
Spread Enable¹
Type
RW
RW
RW
RW
RW
0
1
See Frequency
Selection Table, Page 1
Off
On
Bit 2
Enable Software Control of
-
Frequency, Spread Enable
(Spread Type always Software
RW
Hardware Software
Select
Select
Control)
Bit 1
-
Bit 0
-
DIF_STOP# drive mode
SPREAD TYPE
RW
Driven
Hi-Z
RW
Down
Center
PWD
Pin 27
Pin 5
Pin 44
Pin 7
Pin 26
0
0
0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
I²C Table: Output Enable Register
Byte 1
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
DIF_7
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
0823—04/02/04
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