ICS950905 Datasheet, PDF (9/18 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
Byte 17: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCI_INV
AGP
CPU 0/1_INV
CPU_CS_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
PWD
0
0
0
0
1
0
0
1
Description
PCICLK Phase Inversion bit
AGP Phase Inversion bit
CPU 0/1 Phase Inversion bit
CPU_CS Phase Inversion bit
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
Table 1
Table 2
Div (3:2)
00 01 10 11
Div (1:0)
00
/2 /4 /8 /16
01
/3 /6 /12 /24
10
/5 /10 /20 /40
11
/7 /14 /28 /56
Div (3:2)
00 01 10 11
Div (1:0)
00
/4 /8 /16 /32
01
/3 /6 /12 /24
10
/5 /10 /20 /40
11
/9 /18 /36 /72
Byte 18: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPU_Skew 1
CPU_Skew 0
Reserved
Reserved
CPU_Skew 1
CPU_Skew 0
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
Description
These 2 bits delay the CPUCLKC/T_CS with respect to
CPUCLKC/T (1:0)
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
These 2 bits delay the CPUCLKC/T (1:0) clock with respect to
CPUCLKC/T_CS
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP_Skew 1
AGP_Skew 0
Reserved
Reserved
AGP_Skew 1
AGP_Skew 0
Reserved
Reserved
PWD
Description
1 _{These 2 bits delay the AGP (2:1) with respect to CPUCLK}
0 ^{00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps}
0 Reserved
0 Reserved
0 _{These 2 bits delay the AGP_0 with respect to CPUCLK}
1 ^{00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps}
0 Reserved
0 Reserved
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