ICS950905 Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
Byte 1: CPU Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit7
-
1 (Reserved)
Bit6
10
1 PCICLK_F (Active/Inactive)
Bit5
-
1 (Reserved)
Bit4
-
1 (Reserved)
Bit3
-
0 CPUCLKT/C_CS 1x/2x Strength(1 = 2x, 0 = 1x)
Bit2 35, 34
1 CPUCLKT/C1 (Active/Inactive)
Bit1 40, 39
1 CPUCLKT/C0 (Active/Inactive)
Bit0 42, 41
1 CPUCLKT/C_CS (Active/Inactive)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Bit7
21
1 PCICLK7 (Active/Inactive)
Bit6
19
1 PCICLK6 (Active/Inactive)
Bit5
18
1 PCICLK5 (Active/Inactive)
Bit4
17
1 PCICLK4 (Active/Inactive)
Bit3
15
1 PCICLK3 (Active/Inactive)
Bit2
14
1 PCICLK2 (Active/Inactive)
Bit1
12
1 PCICLK1 (Active/Inactive)
Bit0
11
1 PCICLK0 (Active/Inactive)
Description
Byte 3: Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit7
-
1 Reserved
Bit6
1
1 SEL 24_48, 0=24Mhz 1=48MHz
Bit5
-
1 (Reserved)
Bit4
-
- (Reserved)
Bit3
45
1 IOAPIC 1
Bit2
23
1 AGPCLK 0
Bit1
26
1 AGPCLK 1
Bit0
27
1 AGPCLK 2
Byte 4: Frequency Select Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
-
7
8
-
1
PWD
X
X
X
X
1
1
X
1
Latched FS3#
Latched FS2#
Latched FS1#
Latched FS0#
48MHz (Active/Inactive)
24_48MHz (Active/Inactive)
WDEN (Readback)
REF (Active/Inactive)
Description
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5
ICS950905
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