ICS950905 Datasheet, PDF (1/18 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
Programmable Timing Control Hub™ for P4™
Recommended Application:
VIA P4X266 chipset with PC133 or DDR memory.
Output Features:
• 2 - Pair of differential CPU clocks @ 3.3V
• 1 - Pair of differential push pull CPU_CS clocks @ 2.5V
• 3 - AGP @ 3.3V
• 9 - PCI @ 3.3V
• 1- IOAPIC @ 2.5V
• 1 - 48MHz @ 3.3V fixed
• 1 - 24_48MHz @ 3.3V
• 1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
Pin Configuration
1_{**SEL24_48/REF0}
1
VDDREF 2
GND 3
X1 4
X2 5
VDD48 6
*FS3/48MHz 7
*FS2/24_48MHz
8
GND 9
*FS0/PCICLK_F 10
**FS1/PCICLK0 11
*MULTI_SEL/PCICLK1 12
GND 13
*WDTB/PCICLK2 14
**WDEN/PCICLK3 15
VDDPCI 16
PCICLK4 17
PCICLK5 18
PCICLK6 19
GND 20
PCICLK7 21
*PD# 22
AGPCLK0 23
VDDAGP 24
48 VDDLAPIC
47 GND
46 N/C
45 IOAPIC
44 GND
43 VDDCPU_PP (2.5V)
42 CPUCLK_PPT
41 CPUCLK_PPC
40 CPUCLKT_0
39 CPUCLKC_0
38 VDDCPU (3.3V)
37 I REF
36 GND
35 CPUCLKT_1
34 CPUCLKC_1
33 Vtt_PWRGD#
32 CPU_STOP#*
31 PCI_STOP#*
30 RESET#
29 SDATA
28 SCLK
27 AGPCLK2
26 AGPCLK1
25 GND
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I²C Index read/write and block read/write
operations.
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* These inputs have a internal Pull-up resistor
of 120K to VDD
** These inputs have a internal pull-down to GND
• For DDR and or PC133 SDRAM system use ICS93718 _{Frequency Table}
as the memory buffer.
• Uses external 14.318MHz crystal.
Key Specifications:
FS3
FS2
FS1
FS0
CPUCLK
MHz
AGP
MHz
PCICLK
MHz
• CPU_CS - CPU0: <±250ps
• CPU_CS - AGP: <±250ps
• PCI - PCI: <500ps
• CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Block Diagram
0
0
0 0 160.00 80.00 40.00
0
0
0
1 164.00 82.00
41.00
0
0
1 0 166.60 66.60 33.30
0
0
1 1 170.00 68.00 34.00
0
1
0
0 175.00 70.00
35.00
PLL2
/2
X1
XTAL
X2
OSC
48MHz
24_48MHz
REF0
0
1
0
1 180.00 72.00
36.00
0
1
1 0 185.00 74.00 37.00
0
1
1 1 190.00 76.00 38.00
1
0
0
0 66.80 66.80 33.40
1
0
0
1 100.90 67.27 33.63
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLKT_(1:0)
CPUCLKC_(1:0)
1
0
1 0 133.60 66.80 33.40
1
0
1 1 200.40 66.80 33.40
SEL24_48
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
MULTI_SEL
Vtt_PWRGD#
WDEN
WDTB
Control
Logic
Config.
Reg.
CPU
DIVDER
Stop
IOAPIC
DIVDER
PCI
Stop
DIVDER
AGP
DIVDER
CPUCLK_PPT
CPUCLK_PPC
IOAPIC
PCICLK (7:0)
PCICLK_F
AGPCLK (2:0)
3
RESET#
I REF
1
1
0 0 66.60 66.60 32.30
1
1
0
1 100.00 66.60
33.30
1
1
1 0 200.00 68.60 33.30
1
1
1 1 133.30 68.60 33.30
MULTISEL0
Board Target
Trace/Term Z
0
50 ohms
1
50 ohms
Reference R,
Iref =
V_DD/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Voh @ Z
Ioh = 4* I REF 1.0V @ 50
Ioh = 6* I REF 0.7V @ 50
950905 Rev - 11/26/01
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.