ICS950905 Datasheet, PDF (2/18 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
General Description
The ICS950905 is a single chip clock solution for desktop designs using the VIA P4X266 chipset with PC133 or DDR memory.
with PC133 or DDR memory. When used with a fanout buffer such as the ICS93712, ICS93715 or the ICS93718 provides all
the necessary clock signals for such a system.
The ICS950905 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1
2, 6, 16, 24, 38
4
5
7
PIN NAME
SEL24_48
REF0
VDD
X1
X2
FS3
48MHz
8
3, 9, 13, 20, 25,
36, 44, 47
10
11
14
15
21, 19, 18, 17
FS2
24_48MHz
GND
FS0
PCICLK_F
FS1
PCICLK0
WDTB
PCICLK2
WDEN
PCICLK3
PCICLK (7:4)
22
PD#
27, 26, 23
28
29
30
33
AGP (2:0)
SCLK
SDATA
RESET#
Vtt_PWRGD#
34, 39
CPUCLKC_(1:0)
35, 40
CPUCLKT_(1:0)
37
I REF
41
CPUCLK_PPC
42
CPUCLK_PPT
43
VDDCPU_PP (2.5V)
45
IOAPIC
46
N/C
48
VDDLAPIC
TYPE
DESCRIPTION
IN Lathc input to selects either 24 or 48MHz output. 0 = 24MHz; 1 = 68MHz.
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply.
IN Crystal input, has internal load cap (33pF) and feedback resistor from X2.
OUT Crystal output, nominally 14.318MHz. Has internal load cap (33pF).
IN Logic input frequency select bit. Input latched at power on.
OUT 3.3V Fixed 48MHz clock output..
IN Logic input frequency select bit. Input latched at power on.
OUT Selectable 24 or 48MHz output.
PWR Ground pins for 3.3V supply.
IN
O UT
IN
O UT
IN
O UT
IN
O UT
O UT
IN
O UT
IN
I/O
O UT
IN
O UT
O UT
OUT
OUT
OUT
PWR
OUT
-
PWR
Logic input frequency select bit. Input latched at power on.
3.3V Free running PCI clock output
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output.
Watch dog time base select input. 1 = 290 ms/step; 0 = 580 ms/step.
3.3V PCI clock output.
Hardware enable of watch dog circuit. Default safe frequency is 100MHz. 0 = WD Disable; 1 = WD
Enable. This is a latch input.
3.3V PCI clock output.
3.3V PCI clock outputs.
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power
down will not be greater than 3ms.
AGP outputs defined as 2X PCI. These may not be stopped.
Clock pin for I²C circuitry 5V tolerant.
Data pin for I²C circuitry 5V tolerant.
Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (3:0) and MULTSEL inputs
are valid and are ready to be sampled (active low).
"Complementory" clocks of differential pair CPU outputs. These are current outputs and external
resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and external resistors are
required for voltage bias.
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate current.
Complementory"" clocks of differential pair CPU outputs. These are 2.5V push-pull outputs.
True"" clocks of differential pair CPU outputs. These are 2.5V push-pull outputs.
Power for CPUCLK_CS outputs 2.5V.
2.5V clock outputs
No connections to this pin.
Power for APIC clocks 2.5V.
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