ICS87973I-147 Datasheet, PDF (9/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
V_DD,
V_DDA, V_DDO
LVCMOS
GND
SCOPE
Qx
V_DD
nCLK
V
PP
CLK
Cross Points
V
CMR
-1.65V±5%
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
QFB
V
DDO
2
V
DDO
2
tcycle n
➤
tcycle n+1
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
V
DDO
2
Qx
➤
Qy
V
DDO
2
V
DDO
2
t sk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nCLK
CLK
V_DD
CLK0,
2
CLK1
V_DD
V_DD
EXT_FB
2
EXT_FB
2
➤ t (Ø)
➤_t(Ø)
t (Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET (DIFFERENTIAL)
2V
0.8V
Clock
Outputs
t_R
2V
0.8V
t_F
OUTPUT RISE/FALL TIME
STATIC PHASE OFFSET (LVCMOS)
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
QFB
V
DDO
2
Pulse Width
t
PERIOD
odc = ^{t PW}
t _PERIOD
OUTPUT DUTY CYCLE/ PULSE WIDTH PERIOD
87973DYI-147
www.icst.com/products/hiperclocks.html
9
REV. A AUGUST 26, 2003