ICS87973I-147 Datasheet, PDF (4/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1
2
3
4
5, 26, 27
6
7
8
9, 10
11
Name
GNDI
Type
Power
nMR/OE Input Pullup
FRZ_CLK Input
FRZ_DATA
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
Input
Input
Pullup
Pullup
Pullup
PLL_SEL Input Pullup
REF_SEL Input Pullup
CLK_SEL Input
CLK0,
CLK1
CLK
Input
Input
Pullup
Pullup
Pullup
Description
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs. When
LOW, resets the outputs to tristate and resets output divide circuitry.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Configuration data input for freeze circuitry.
LVCMOS / LVTTL interface levels.
Select pins control Feedback Divide value.
LVCMOS / LVTTL interface levels.
Selects between the PLL and reference clocks as the input to the output
dividers. When HIGH, selects PLL. When LOW, bypasses the PLL.
LVCMOS / LVTTL interface levels.
Selects between CLK0 or CLK1 and CLK, nCLK inputs.
When HIGH, selects CLK, nCLK. When LOW, selects CLK0 or CLK1.
LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 and CLK1 as phase detector
reference. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
Reference clock inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
12
nCLK
Input
13
V_DDA
Power
14
INV_CLK Input
15, 24, 30,
35, 39, 47, 51
16, 18,
21, 23
17, 22, 33,
37, 45, 49
19, 20
GNDO
QC3, QC2,
QC1, QC0
V_DDO
FSEL_C1,
FSEL_C0
Power
Output
Power
Input
25
QSYNC Output
28
V
Power
DD
29
QFB Output
Pullup
Pullup
Inverting differential clock input. V_DD/2 default when left floating.
Analog supply pin.
Inverted clock select for QC2 and QC3 outputs.
LVCMOS / LVTTL interface levels.
Power supply ground.
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins.
Select pins for Bank C outputs. LVCMOS / LVTTL interface levels.
Synchronization output for Bank A and Bank C. Refer to Figure 1,
Timing Diagrams. LVCMOS / LVTTL interface levels.
Core supply pins.
Feedback clock output. LVCMOS / LVTTL interface levels.
31
EXT_FB Input Pullup Extended feedback. LVCMOS / LVTTL interface levels.
32, 34,
36, 38
40, 41
42, 43
44, 46,
48, 50
52
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
Output
Input
Input
Output
VCO_SEL Input
Pullup
Pullup
Pullup
Bank B clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Select pins for Bank B outputs. LVCMOS / LVTTL interface levels.
Select pins for Bank A outputs. LVCMOS / LVTTL interface levels.
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1.
When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.
NOTE: Pullup refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
87973DYI-147
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REV. A AUGUST 26, 2003