ICS87973I-147 Datasheet, PDF (8/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 6. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
÷2
150
÷4
f_MAX
Output Frequency
÷6
125
83.33
÷8
62.5
CLK0
-10
145
300
t(Ø)
Static Phase Offset;
NOTE 1
CLK1
QFB ÷8
-65
In Frequency = 50MHz
90
245
CLK, nCLK
-130
18
165
tsk(o) Output Skew; NOTE 2
200
tjit(cc) Cycle-to-Cycle Jitter; NOTE 3, 4
All Banks ÷ 4
55
f_VCO
PLL VCO Lock Range
240
500
t_LOCK
PLL Lock Time; NOTE 3
10
t /t
Output Rise/Fall Time
0.8V to 2V
150
700
RF
odc
Output Duty Cycle
45
55
t_PZL, t_PZH Output Enable Time; NOTE 3
2
10
t_PLZ, t_PHZ Output Disable TIme; NOTE 3
2
8
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
MHz
mS
ps
%
ns
ns
87973DYI-147
www.icst.com/products/hiperclocks.html
8
REV. A AUGUST 26, 2003