ICS8523I Datasheet, PDF (9/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8523I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V_SWING and V_OH must meet the V_PP
and V_CMR input requirements. Figures 4A to 4F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver ter-
mination requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK _HiPerClockS
PCLK/nPCLK
3.3V
Zo = 50 Ohm
3.3V
R1
PCLK
100
nPCLK
Zo = 50 Ohm
HiPerClockS
CML Built-In Pullup
PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
Zo = 50 Ohm
LVPEC L
Zo = 50 Ohm
3. 3V
R3
R4
125
125
3.3V
PCLK
nPCLK _HiPerClockS
Input
R1
R2
84
84
3.3V
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R3
R4
84
84
C1
C2
R5
100 - 200
R6
100 - 200
R1
R2
125
125
3.3V
PCLK
nPCLK _HiPerClockS
PCLK/nPCLK
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
3.3V
LVDS
Zo = 50 Ohm
R5
100
Zo = 50 Ohm
3.3V
3.3V
R3
R4
1K
1K
C1
PCLK
C2
nPCLK
HiPerClockS
PC L K / n PC L K
R1
R2
1K
1K
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
8523BGI
www.icst.com/products/hiperclocks.html
9
REV. C SEPTEMBER 16, 2004