ICS8523I Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8523I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
GND
Power
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
2
CLK_EN
Input
Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential PCLK, nPCLK
3
CLK_SEL
Input Pulldown inputs. When LOW, selects CLK, nCLK inputs.
LVCMOS / LVTTL interface levels.
4
CLK
Input Pulldown Non-inverting differential clock input.
5
nCLK
Input
Pullup Inverting differential clock input.
6
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
7
nPCLK
Input
Pullup Inverting differential LVPECL clock input.
8, 9
nc
Unused
No connect.
10
11, 12
V
DD
nQ3, Q3
Power
Output
Core supply pin.
Differential output pair. HSTL interface levels.
13, 18
14, 15
V_DDO
nQ2, Q2
Power
Output
Output supply pins.
Differential output pair. HSTL interface levels.
16, 17
nQ1, Q1
Output
Differential output pair. HSTL interface levels.
19, 20
nQ0, Q0
Output
Differential output pair. HSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R
PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8523BGI
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2
REV. C SEPTEMBER 16, 2004