ICS8523I Datasheet, PDF (5/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8523I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical
PCLK
I_IH
Input High Current
nPCLK
V_DD = V_IN = 3.465V
V_DD = V_IN = 3.465V
PCLK
I_IL
Input Low Current
nPCLK
V_DD = 3.465V, V_IN = 0V
V_DD = 3.465V, V_IN = 0V
-5
-150
V_PP
Peak-to-Peak Input Voltage
0.3
V_CMR
Common Mode Input Voltage; NOTE 1, 2
1.5
NOTE 1: Common mode voltage is defined as V_IH.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is V_DD + 0.3V.
Maximum
150
5
1
V_DD
Units
µA
µA
µA
µA
V
V
TABLE
4D.
HSTL
DC
CHARACTERISTICS,
V
DD
=
3.3V±5%,
V
DDO
=
1.8V±0.2V,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
V_OH
Output High Voltage;
NOTE 1
V_OL
Output Low Voltage;
NOTE 1
0.9
1.4
0
0.4
V_OX
V_SWING
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
40% x (V_OH - V_OL) + V_OL
0.6
60% x (V_OH - V_OL) + V_OL
1.3
NOTE 1: Outputs terminated with 50Ω to ground.
Units
V
V
V
V
TABLE 5. AC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
650
t_PD
Propagation Delay; NOTE 1
IJ 650MHz
1.0
1.6
tsk(o) Output Skew; NOTE 2, 4
50
tsk(pp) Part-to-Part Skew; NOTE 3, 4
250
t_R
Output Rise Time
20% to 80% @ 50MHz
300
700
t
Output Fall Time
20% to 80% @ 50MHz
300
700
F
odc
Output Duty Cycle
45
55
All parameters measured at 500MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ps
%
8523BGI
www.icst.com/products/hiperclocks.html
5
REV. C SEPTEMBER 16, 2004