ICS8523I Datasheet, PDF (1/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8523I
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8523I is a low skew, high perfor-
mance 1-to-4 Differential-to-HSTL fanout buffer
HiPerClockS™ _{and a member of the HiPerClockS™family of High}
Performance Clock Solutions from ICS. The
ICS8523I has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8523I ideal for those applications demanding
well defined performance and repeatability.
FEATURES
• 4 differential HSTL compatible outputs
• Selectable diffferential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to HSTL
levels with resistor bias on nCLK input
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.6ns (maximum)
• 3.3V core, 1.8V output operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
CLK_EN
CLK
nCLK
0
PCLK
nPCLK
1
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
GND 1 20 Q0
CLK_EN 2 19 nQ0
CLK_SEL ³
1 8 _VDDO
CLK 4 ¹⁷ Q1
Q0
nCLK 5 16 nQ1
nQ0
PCLK ^{6 15} Q2
Q1
nQ1
nPCLK 7
nc 8
nc ⁹
14 _nQ2
1 3 _VDDO
12 _Q3
Q2
VDD 10 ¹¹ nQ3
nQ2
ICS8523I
Q3
20-Lead TSSOP
nQ3
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
8523BGI
www.icst.com/products/hiperclocks.html
1
REV. C SEPTEMBER 16, 2004