ICS8432I-101 Datasheet, PDF (9/18 Pages) Integrated Circuit Systems – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8432I-101
700MHZ,
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched impedance
techniques should be used to maximize operating frequency
and minimize signal distortion. Figures 4A and 4B show two
different layouts which are recommended only as guidelines.
Other suitable clock layouts may exist and it would be rec-
ommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component
process variations.
Z_o = 50Ω
3.3V
125Ω
125Ω
FOUT
FIN
Z_o = 50Ω
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
Z_o = 50Ω
84Ω
FIN
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
8432DYI-101
www.icst.com/products/hiperclocks.html
REV. A MAY 23, 2005
9