ICS8432I-101 Datasheet, PDF (3/18 Pages) Integrated Circuit Systems – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8432I-101
700MHZ,
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
2, 3, 4
28, 29
30, 31, 32
5, 6
7
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
Input
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transistion
Pulldown ^{of nP_LOAD input. LVCMOS / LVTTL interface levels.}
Input
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
Unused
No connect.
8, 16
9
10
11, 12
V_EE
TEST
Power
Output
V_CC
Power
FOUT1, nFOUT1 Output
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
Core supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
13
14, 15
V
CCO
Power
FOUT0, nFOUT0 Output
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
17
MR
Input Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
18
S_CLOCK
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
19
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
20
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
21
V_CCA
Power
Analog supply pin.
Clock select input. Selects between differential clock input or
22
CLK_SEL
Input
Pullup
TEST_CLK input as the PLL reference source. When HIGH,
selects CLK, nCLK inputs. When LOW, selects TEST_CLK input.
LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input Pulldown Test clock input. LVCMOS / LVTTL interface levels.
24
CLK
Input Pulldown Non-inverting differential clock input.
25
nCLK
Input Pullup Inverting differential clock input.
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterisitics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
8432DYI-101
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
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3
REV. A MAY 23, 2005