ICS8432I-101 Datasheet, PDF (6/18 Pages) Integrated Circuit Systems – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8432I-101
700MHZ,
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum
Units
CLK
I_IH
Input High Current
nCLK
V_CC = V_IN = 3.465V
V_CC = V_IN = 3.465V
I_IL
CLK
Input Low Current
nCLK
V_CC = 3.465V, V_IN = 0V
V_CC = 3.465V, V_IN = 0V
-5
-150
V_PP
Peak-to-Peak Input Voltage
0.15
V_CMR
Common Mode Input Voltage
V_EE + 0.5
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V_CC + 0.3V.
NOTE 2: Common mode voltage is defined as V_IH.
150
5
1.3
V_CC - 0.85
TABLE
4D.
LVPECL
DC
CHARACTERISTICS,
V
CC
=
V
CCA
=
V
CCO
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
µA
µA
µA
µA
V
V
Units
V_OH
Output High Voltage; NOTE 1
V_OL
Output Low Voltage; NOTE 1
V_SWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to V_CCO - 2V.
V_CCO - 1.4
V_CCO - 2.0
0.6
V_CCO - 0.9
V
V_CCO - 1.7
V
1.0
V
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
14
25
MHz
f_IN
Input Frequency CLK, nCLK; NOTE 1
S_CLOCK
14
25
MHz
25
MHz
NOTE 1: For the differential input and TEST_CLK frequency range, the M value must be set for the VCO to operate within
the 250MHz to 700MHz range. Using the minimum input frequency of 14MHz, valid values of M are 18 ≤ M ≤ 50.
Using the maximum frequency of 25MHz, valid values of M are 10 ≤ M ≤ 28.
TABLE 6. AC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
F_OUT
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1, 3
fVCO > 350MHz
31.25
700
MHz
25
ps
tjit(per) Period Jitter, RMS; NOTE 1
fOUT > 100MHz
5
ps
tsk(o) Output Skew; NOTE 2, 3
15
ps
t_R / t_F
Output Rise/Fall Time
20% to 80%
200
M, N to nP_LOAD
5
700
ps
ns
t_S
Setup Time S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
t_H
Hold Time S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
odc
Output Duty Cycle
N>1
47
53
%
t_PW
Output Pulse Width
N=1
t_PERIOD/2 - 150
t_PERIOD/2 + 150 ps
t
LOCK
PLL Lock Time
See Parameter Measurement Information section.
1
ms
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8432DYI-101
www.icst.com/products/hiperclocks.html
REV. A MAY 23, 2005
6